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The I7 Intel: internal structure

Released in 2008, I7 is a computer processor quad-core desktop applications but also server specific characteristics compared to its predecessors as the Core2 Duo. It is based on an entirely new architecture, Nehalem and accepting modes 32 and 64 bits following the instructions of Intel EM64T (equivalent to AMD's AMD64 ISA).

First feature, the I7 directly integrates the memory controller (like the Athlon 64 and Phenom since 2004) but on 3 channels. It manages DDR3 Ram until 1066 MHz Dual Channel (so 6 memories modules). This reduces the latency memory access since there is the Northbridge chipset as an intermediary. The socket is new (LGA1366) with a new system for setting the cooler.

The second characteristic is the Management of the 4 cores integrated into the microprocessor. In the Core 2 Duo, clock speed is identical for all present Core. In these new processors can handle frequencies of each individual core, including one or more overclock core during a low period if others do not work or less. It is the Turbo mode under the IDA used in some models of processors for notebook PCs.

The third feature is related to the cache management. In a Core2 Duo processor, two processors are finally joined together simply with one another as in the diagram cons with well-defined L2 caches. Instead, I7 handles 4 processors as a single whole.

Found for each processor L1 cache of 32 KB for instructions and 32 KB for data (same as Core 2 Duo) L2 cache integrated into each Core 256 KB, but especially a shared cache of 8 MB is in Wholesale 2 MB per core. The L1 and L2 caches are also copied to the L3 cache to allow a real sharing of information. This also allows the sharing of data in different cache among all the hearts of I7.

The fourth characteristic is linked to a new bus, QPI (QuickPath Interconnect) similar to Hyper-Transport AMD manages external communications to the northbridge but perhaps also in multiprocessor future developments. This new bus connects the CPU to Northbridge with loan of 4.8 gigabytes transfer per second  to the bus via a total of 20 bidirectional channels, ie effective data rate of 4.8 X 20 / 8 = 12 GB / s (a 6.4 Giga transfers - GT / s - is announced).

It could be just the processor but incorporates many other surprises as integrated virtualization. Necessary for future applications but especially retrour of the Hyper-Threading implanted in the latest Pentium IV and then removed in the Intel Core used which ultimately improved architecture of a Pentium III, so difficult to modify. Hyper-Threading allows to manage two logical processors in one heart to win (if the application is designed for) 30% performance.

At level chipset, only the X58 Intel is currently on the market. SLI technology can be implemented on motherboards as the chip accepts a 2-channel 16-port PCI-Express 2.0 mode (more than 6 ports on the Southbridge (the Intel ICH10 in this case)).

The first three versions are:

and the Extreme Edition series (June 2009), the transfer bus speed is increased from 4.8 Giga transactions per second at 6.4.

Then come along with the output of the I5 in September 2009 and using the Socket LGA1156 and the P55 chipset (therefore some limitations since it uses it the "old bus" DMI to connect southbridge is the P55) but also opportunities turbo modified: therefore less efficient with no Dual PCI Express for video cards.

Only default, it's price ....

Other Intel microprocessors: I5, Pentium - MMX - Pentium 2, 3 and 4 - Intel Core - 4004 (first microprocessor) - 8086 - 8088 - 80286 - 80386 - 80486 - Itanimum (decated server)

More definitions: PCI Express bus, Caches L1, L2 and L3, Speedstep (reduce frequency), DDR3 memories

Last update, 02/20/2017
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