L1 cache

The cache L1 is located directly in Microprocessor. It contains the assembly instructions and data most often used . Is the processor that manages content .

L1 cache appeared with the first Intel Pentium. At the time , its capacity was 8 KB for data and 8 KB for instructions . The evolution of the internal structure of processors moved it to 32 KB ( 16 + 16 ) for the Pentium MMX and 128 KB (64 + 64) for current processors such as Athlon 64.

Optimal use is mainly related to branch prediction . While the program is linear , without choice possible , the list of instructions stored does not pose a problem . By cons , in case of connection (a conditional instruction for example ), if the content of the memory is false , the list of "cached" instruction should be completely recharged. This reduced performance.

The use of instruction cache is especially related to structure pipeline modern processors . The Pentium IV (architecture superpipeline - Netburst) no longer use this method directly , but a predecoded instruction list in RISC called "Instruction Trace Cache " allowing up to 12,000 instructions.

Improved performance by this buffer is difficult to assess, even if it is possible in some BIOS to configure processor to work without that memory.