Appearing for the PC processor servers with Itanium
in 2001 and for stations with the AMD Athlon64, 64-bit technology is based on an
internal architecture of the microprocessor using registers (internal memory)
with a width of 64 bits (8 bytes ) for instructions and data (including the
integers caculs).
Since the Pentium, the external data bus is also a
width of 64. Unfortunately, internal registers that can operate 32 data and
instructions. Basically, the instructions received from RAM are twice as large
as those handled by the Microprocessor
who must use two clock cycles. At the same time, the CPU can not directly refer
to the bus but must eventually complete the message to send over two cycles.
These 32-bit registers have also another
disadvantage on the address bus, the processor can address only 232
different addresses, or 4 GB of memory maximum. This is the case since the 386,
even if Windows XP and less can manage only maximum 3 GB.
The addition of 64-bit processor will finally deal
with instructions in a single pass through the internal registers and exceed the
limit of addressing 4 GB of RAM. The current operating systems are optimized for
those instructions 32. The use of 64 modes requires an operating system
(Windows, Linux, MacOS, ...) recompiled to allow a higher memory address and
manage new specific instructions.
Two solutions were adopted:
With Intel Itanium rewrote the command processor. This solution
was first advantage of using a new internal architecture IA64-based EPIC
more efficient, then no longer pass through a converter in X86 instructions CISC
treatment to domestic RISC
since orders are no longer based on history. L 'Itanium
(II) allows for example to execute 3 instructions to do exactly the same
work as 5 instructions legacy, where a famous processing gain and therefore
speed. But ... This method has the disadvantage of making the processor
Itanimum incompatible with older operating systems and software to 32, where
an OS and specific software. Only some versions of Windows 2003-2008 servers
accept (Enterprise and Data Center Editon). 32 emulators exist but
are inefficient.
Basically: performance against incompatibility.
AMD's Opteron - Sempron / Athlon
64 / Phenom / Core 2 used another method, transforming the standard architecture (or rather
adapted). Besides lengthening the internal registers from 32 to 64, these
processors based on the MIPS64 instruction set ™ run a higher address. The
internal architecture is slightly modified, the instructions are ultimately
the same ... This technology handles are two modes. At startup, the next
operating system, the processor will go to either. The advantage is the
compatibility with older 32-bit operating systems. In 64-some specific instructions
are used, others used the X86 are removed. Various additional registers are
also used, particularly in media with SSE
instructions. This second method also requires operating systems and
specific software, but simply recompiled to reflect some changes. The Xeon
32/64 uses exactly the same idea and the same instructions. Using a
microprocessor of this type with Vista
32 is exactly the same for an Intel Core 1 incompatible (core 2 and next
like I5 and I7 are 64
bits compatibles)
Basically: Compatibility against performance although the majority of
32-bit software does not work on this type of operating system.
